Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device.
Description of the Background Art
A semiconductor device including plural types of circuit patterns such as memory cells, for example, has been known. In such a semiconductor device, a plurality of level difference portions (such as various electrodes) provided to project with respect to a main surface of a semiconductor substrate are formed. Arrangement of the level difference portions in a semiconductor device is different for each circuit pattern. Generally, a semiconductor device includes a region in which the level difference portions are formed relatively densely (hereinafter referred to as a first region), and a region in which the level difference portions are formed relatively sparsely or a region in which no level difference portion is formed (hereinafter referred to as a second region). A method for manufacturing such a semiconductor device includes the step of forming various films on and between the level difference portions formed on a semiconductor substrate, and the step of processing the films (such as a photolithography step or an etch-back treatment step).
The photolithography step is disclosed, for example, in Japanese Patent Laying-Open No. 2010-245160 (Patent Document 1), and US Patent Application Publication No. 2004/0065917 (Patent Document 2). Patent Document 1 discloses a method for manufacturing a semiconductor device for solving a problem caused when an anti-reflection film applied in a region having a high level difference flows to a region having a low level difference and disappears. Specifically, in Patent Document 1, a dummy electrode and a polysilicon film serving as level difference portions are formed with a gap groove being sandwiched therebetween. Thus, when an anti-reflection film having a high flowability is applied on a polysilicon film formed to cover these components, disappearance of the anti-reflection film in the region having a high level difference is suppressed.
US Patent Application Publication No. 2004/0065917 discloses a memory cell having a transistor structure different from that of Patent Document 1, and a method for manufacturing the same. Also in the method for manufacturing the memory cell described in Patent Document 2, the first region and the second region described above are formed.